1. Field of the Invention
The present invention relates to phasing receivers and particularly, but not exclusively to polyphase or sequence-asymmetric receivers which may be implemented as an integrated circuit.
2. Description of the Related Art
A popular type of architecture for use as an integrated receiver is a zero-IF architecture in which an input signal is frequency downconverted to a zero-IF using quadrature mixers, the wanted signals are selected from the products of mixing using low pass filters and the wanted signals are processed further to provide a demodulated output.
Most of the limitations which beset the zero-IF receiver arise either directly or indirectly from the fact that components of wanted signals translated down to IF frequencies at or around DC cannot be distinguished from components of unwanted signals which appear in the same frequency range as a result of inherent circuit deficiencies.
The above-mentioned limitations in a zero-IF receiver may be eliminated substantially in a low-IF superheterodyne receiver but this would suffer from an image response that could not be eliminated by realistic front-end filters.
Another receiver architecture termed a phasing receiver, is a low-IF receiver based on the principle of the image-reject mixer in which the image response is removed by cancellation, rather than filtering, but the level of image rejection which can be achieved, even in fully-integrated form, is severely limited by the degree of matching which can be obtained between nominally identical components. A particular example of a phasing receiver is the polyphase or sequence-asymmetric receiver in which the conventional IF filters, IF phase shifters and IF signal combiner are replaced by a single polyphase IF filter. This very substantially increases the level of image rejection which can be obtained. In spite of the increased level of image rejection there may still a need to improve further the level of image rejection.